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| 1. general description the 74lvc4066-q100 is a high-speed si-gate cmos device. the 74lvc4066-q100 provides four single pole, single-throw analog switch functions. each switch has two input/output terminals (ny and nz) and an active high enable input (ne). when ne is low, the analog switch is turned off. schmitt-trigger action at the enable inputs make s the circuit tolerant of slower input rise and fall times across the entire v cc range from 1.65 v to 5.5 v. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide supply voltage range from 1.65 v to 5.5 v ? very low on resistance: ? 7.5 ? (typical) at v cc = 2.7 v ? 6.5 ? (typical) at v cc = 3.3 v ? 6 ? (typical) at v cc = 5 v ? switch current ca pability of 32 ma ? high noise immunity ? cmos low-power consumption ? direct interface ttl-levels ? latch-up performance exceeds 250 ma ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? enable inputs accept voltages up to 5 v ? multiple package options 74lvc4066-q100 quad bilateral switch rev. 1 ? 7 august 2012 product data sheet
74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 2 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74lvc4066d-q100 ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74LVC4066PW-Q100 ? 40 ? c to +125 ? c tssop14 plastic thin small outline package; 14 leads; body width 4.4 mm sot402-1 74lvc4066bq-q100 ? 40 ? c to +125 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1 fig 1. logic symb ol fig 2. logic symbol (ieee/iec) mnb111 1y 1z 12 2y 2z 43 1e13 3y 3z 89 4y 4z 11 10 3e6 4e 12 2e5 mnb112 12 13 # 43 5# 89 6# 11 10 (a) 12 # 12 13 1 x1 1 x1 1 x1 1 1 1 1 1 x1 # 43 5# 89 6# 11 10 (b) 12 # fig 3. logic diagram (one switch) mna658 v cc ne ny nz 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 3 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch 5. pinning information 5.1 pinning 5.2 pin description (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 4. pin configuration for so14 and tssop14 fig 5. pin configuration for dhvqfn14 ! " # $ %& table 2. pin description symbol pin description 1y 1 independent input/output 1z 2 independent output/input 2z 3 independent output/input 2y 4 independent input/output 2e 5 enable input (active high) 3e 6 enable input (active high) gnd 7 ground (0 v) 3y 8 independent input/output 3z 9 independent output/input 4z 10 independent output/input 4y 11 independent input/output 4e 12 enable input (active high) 1e 13 enable input (active high) v cc 14 supply voltage 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 4 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch 6. functional description [1] h = high voltage level; l = low voltage level. 7. limiting values [1] the minimum input voltage rating may be exceeded if the input current rating is observed. [2] the minimum and maximum switch voltage ratings may be e xceeded if the switch clamping current rating is observed. [3] for so14 packages: above 70 ? c derate linearly with 8 mw/k. for tssop14 packages: above 60 ? c derate linearly with 5.5 mw/k. for dhvqfn14 packages: above 60 ? c derate linearly with 4.5 mw/k. table 3. function table [1] input ne switch loff hon table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +6.5 v v i input voltage [1] ? 0.5 +6.5 v i ik input clamping current v i < ? 0.5 v or v i 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 6 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch [1] all typical values are measured at t amb =25 ? c. [2] these typical values are measured at v cc =3.3v. 9.1 test circuits 9.2 on resistance c i input capacitance - 12.5 - - - pf c s(off) off-state capacitance -8.0- - -pf c s(on) on-state capacitance - 14.0 - - - pf table 6. static characteristics ?continued at recommended operating conditions voltages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max v i = v cc or gnd and v o = gnd or v cc .v i = v cc or gnd and v o = open circuit. fig 6. test circuit for measuring off-state leakage current fig 7. test circuit for measuring on-state leakage current 001aag488 i s v i v il v o v cc gnd ny nz ne 001aag489 i s v i v ih v o v cc gnd ny nz ne table 7. on resistance at recommended operating conditions; voltages ar e referenced to gnd (ground 0 v); for graphs see figure 9 to figure 14 . symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max r on(peak) on resistance (peak) v i =gndtov cc ; see figure 8 i sw =4ma; v cc = 1.65 v to 1.95 v - 34.0 130 - 195 ? i sw =8ma; v cc = 2.3 v to 2.7 v - 12.0 30 - 45 ? i sw =12ma; v cc = 2.7 v - 10.4 25 - 38 ? i sw =24ma; v cc = 3 v to 3.6 v - 7.8 20 - 30 ? i sw =32ma; v cc = 4.5 v to 5.5 v - 6.2 15 - 23 ? 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 7 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch [1] typical values are measured at t amb = 25 ? c and nominal v cc . [2] flatness is defined as the difference between the maximum and minimum value of on resistance measured at identical v cc and temperature. r on(rail) on resistance (rail) v i = gnd; see figure 8 i sw =4ma; v cc = 1.65 v to 1.95 v -8.218 - 27 ? i sw =8ma; v cc = 2.3 v to 2.7 v - 7.1 16 - 24 ? i sw =12ma; v cc = 2.7 v - 6.9 14 - 21 ? i sw =24ma; v cc = 3 v to 3.6 v - 6.5 12 - 18 ? i sw =32ma; v cc = 4.5 v to 5.5 v - 5.8 10 - 15 ? v i =v cc ; see figure 8 i sw =4ma; v cc = 1.65 v to 1.95 v - 10.4 30 - 45 ? i sw =8ma; v cc = 2.3 v to 2.7 v - 7.6 20 - 30 ? i sw =12ma; v cc = 2.7 v - 7.0 18 - 27 ? i sw =24ma; v cc = 3 v to 3.6 v - 6.1 15 - 23 ? i sw =32ma; v cc = 4.5 v to 5.5 v - 4.9 10 - 15 ? r on(flat) on resistance (flatness) v i =gndtov cc [2] i sw =4ma; v cc = 1.65 v to 1.95 v -26.0- - - ? i sw =8ma; v cc = 2.3 v to 2.7 v - 5.0 - - - ? i sw =12ma; v cc =2.7v - 3.5 - - - ? i sw =24ma; v cc =3vto3.6v - 2.0 - - - ? i sw =32ma; v cc = 4.5 v to 5.5 v - 1.5 - - - ? table 7. on resistance ?continued at recommended operating conditions; voltages ar e referenced to gnd (ground 0 v); for graphs see figure 9 to figure 14 . symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 8 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch 9.3 on resistance test circuit and graphs r on =v sw / i sw .( 1 ) v cc = 1.8 v. (2) v cc = 2.5 v. (3) v cc = 2.7 v. (4) v cc = 3.3 v. (5) v cc = 5.0 v. fig 8. test circuit for measuring on resistance fig 9. typical on resistance as a function of input voltage; t amb = 25 ?c 001aag490 v i v ih v cc gnd nz ny ne v sw i sw v i (v) 05 4 23 1 mna673 20 10 30 40 r on () 0 (1) (2) (3) (4) (5) (1) t amb = 125 ? c. (2) t amb =85 ? c. (3) t amb =25 ? c. (4) t amb = ?40 ? c. (1) t amb = 125 ? c. (2) t amb =85 ? c. (3) t amb =25 ? c. (4) t amb = ?40 ? c. fig 10. on resistance as a function of input voltage; v cc =1.8v fig 11. on resistance as a function of input voltage; v cc =2.5v v i (v) 0 2.0 1.6 0.8 1.2 0.4 001aaa712 25 35 15 45 55 r on () 5 (4) (3) (2) (1) v i (v) 0 2.5 2.0 1.0 1.5 0.5 001aaa708 9 11 7 13 15 r on () 5 (1) (2) (3) (4) 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 9 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch (1) t amb = 125 ? c. (2) t amb =85 ? c. (3) t amb =25 ? c. (4) t amb = ?40 ? c. (1) t amb = 125 ? c. (2) t amb =85 ? c. (3) t amb =25 ? c. (4) t amb = ?40 ? c. fig 12. on resistance as a function of input voltage; v cc =2.7v fig 13. on resistance as a function of input voltage; v cc =3.3v 001aaa709 v i (v) 0 3.0 2.0 1.0 2.5 1.5 0.5 9 7 11 13 r on () 5 (1) (2) (3) (4) v i (v) 04 3 12 001aaa710 6 8 10 r on () 4 (1) (2) (3) (4) (1) t amb = 125 ? c. (2) t amb =85 ? c. (3) t amb =25 ? c. (4) t amb = ?40 ? c. fig 14. on resistance as a function of input voltage; v cc =5.0v v i (v) 05 4 23 1 001aaa711 5 4 6 7 r on () 3 (2) (4) (1) (3) 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 10 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch 10. dynamic characteristics [1] typical values are measured at t amb =25 ? c and nominal v cc . [2] t pd is the same as t plh and t phl . [3] propagation delay is the calculated rc time constant of the typical on resistance of the switch and the specified capacitanc e when driven by an ideal voltage source (zero output impedance). [4] t en is the same as t pzh and t pzl . [5] t dis is the same as t plz and t phz . [6] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? {(c l +c s(on) ) ? v cc 2 ? f o } where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; c s(on) = maximum on-state switch capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? {(c l +c s(on) ) ? v cc 2 ? f o } = sum of the outputs. table 8. dynamic characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v); for load circuit figure 17 . symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max t pd propagation delay ny to nz or nz to ny; see figure 15 [2] [3] v cc = 1.65 v to 1.95 v - 0.8 2.0 - 3.0 ns v cc = 2.3 v to 2.7 v - 0.4 1.2 - 2.0 ns v cc = 2.7 v - 0.4 1.0 - 1.5 ns v cc = 3.0 v to 3.6 v - 0.3 0.8 - 1.5 ns v cc = 4.5 v to 5.5 v - 0.2 0.6 - 1.0 ns t en enable time ne to ny or nz; see figure 16 [4] v cc = 1.65 v to 1.95 v 1.0 5.3 10 1.0 12.5 ns v cc = 2.3 v to 2.7 v 1.0 3.0 5.6 1.0 7.0 ns v cc = 2.7 v 1.0 2.6 5.0 1.0 6.5 ns v cc = 3.0 v to 3.6 v 1.0 2.5 4.4 1.0 5.5 ns v cc = 4.5 v to 5.5 v 1.0 1.9 3.9 1.0 5.0 ns t dis disable time ne to ny or nz; see figure 16 [5] v cc = 1.65 v to 1.95 v 1.0 4.2 9.0 1.0 11.5 ns v cc = 2.3 v to 2.7 v 1.0 2.4 5.5 1.0 7.0 ns v cc = 2.7 v 1.0 3.6 6.5 1.0 8.5 ns v cc = 3.0 v to 3.6 v 1.0 3.4 6.0 1.0 7.5 ns v cc = 4.5 v to 5.5 v 1.0 2.5 5.0 1.0 6.5 ns c pd power dissipation capacitance c l =50pf; f i =10mhz; v i =gndtov cc [6] v cc =2.5v - 11.0 - - - pf v cc = 3.3 v - 12.5 - - - pf v cc = 5.0 v - 15.6 - - - pf 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 11 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch 10.1 waveforms and test circuit measurement points are given in ta b l e 9 . logic levels: v ol and v oh are typical output voltage levels that occur with the output load. fig 15. input (ny or nz) to output (nz or ny) propagation delays 001aaa541 t plh t phl v m v m v m v m ny or nz input nz or ny output gnd v i v oh v ol measurement points are given in ta b l e 9 . logic levels: v ol and v oh are typical output voltage levels that occur with the output load. fig 16. enable and disable times 001aaa542 t plz t phz switch disabled switch enabled switch enabled output low-to-off off-to-low output high-to-off off-to-high ne input ny or nz ny or nz v i v ol v oh v cc v m v m v x v y v m gnd gnd t pzl t pzh table 9. measurement points supply voltage input output v cc v m v m v x v y 1.65 v to 1.95 v 0.5v cc 0.5 v cc v ol + 0.15 v v oh ? 0.15 v 2.3 v to 2.7 v 0.5v cc 0.5v cc v ol + 0.15 v v oh ? 0.15 v 2.7v 1.5v 1.5v v ol + 0.3 v v oh ? 0.3 v 3.0vto3.6v 1.5v 1.5v v ol + 0.3 v v oh ? 0.3 v 4.5 v to 5.5 v 0.5v cc 0.5v cc v ol + 0.3 v v oh ? 0.3 v 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 12 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch 10.2 additional dynami c characteristics test data is given in table 10 . definitions test circuit: r t = termination resistance should be equal to output impedance z o of the pulse generator. c l = load capacitance including jig and probe capacitance. r l = load resistance. v ext = external voltage for measuring switching times. fig 17. load circuit for switching times v ext v cc v i v o mna616 dut c l r t r l r l g table 10. test data supply voltage input load v ext v cc v i t r , t f c l r l t plh , t phl t pzh , t phz t pzl , t plz 1.65 v to 1.95 v v cc ? 2.0ns 30pf 1k ? open gnd 2v cc 2.3 v to 2.7 v v cc ? 2.0ns 30pf 500 ? open gnd 2v cc 2.7 v 2.7 v ? 2.5ns 50pf 500 ? open gnd 6 v 3.0 v to 3.6 v 2.7 v ? 2.5ns 50pf 500 ? open gnd 6 v 4.5 v to 5.5 v v cc ? 2.5ns 50pf 500 ? open gnd 2v cc table 11. additional dynamic characteristics at recommended operating conditions; voltag es are referenced to gnd (ground = 0 v); t amb =25 ? c. symbol parameter conditions min typ max unit thd total harmonic distortion r l = 10 k ? ; c l = 50 pf; f i = 1 khz; see figure 18 v cc = 1.65 v - 0.032 - % v cc = 2.3 v - 0.008 - % v cc = 3 v - 0.006 - % v cc = 4.5 v - 0.005 - % r l = 10 k ? ; c l = 50 pf; f i =10khz; see figure 18 v cc = 1.65 v - 0.068 - % v cc = 2.3 v - 0.009 - % v cc = 3 v - 0.008 - % v cc = 4.5 v - 0.006 - % 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 13 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch f (|-3db) |-3 db frequency response r l = 600 ? ; c l = 50 pf; see figure 19 v cc = 1.65 v - 170 - mhz v cc = 2.3 v - 210 - mhz v cc = 3 v - 212 - mhz v cc = 4.5 v - 215 - mhz r l = 50 ? ; c l = 5 pf; see figure 19 v cc = 1.65 v - > 500 - mhz v cc = 2.3 v - > 500 - mhz v cc = 3 v - > 500 - mhz v cc = 4.5 v - > 500 - mhz ? iso isolation (off-state) r l = 600 ? ; c l = 50 pf; f i = 1 mhz; see figure 20 v cc = 1.65 v - ? 46 - db v cc = 2.3 v - ? 46 - db v cc = 3 v - ? 46 - db v cc = 4.5 v - ? 46 - db r l = 50 ? ; c l = 5 pf; f i = 1 mhz; see figure 20 v cc = 1.65 v - ? 42 - db v cc = 2.3 v - ? 42 - db v cc = 3 v - ? 42 - db v cc = 4.5 v - ? 42 - db v ct crosstalk voltage between digital inputs and switch; r l = 600 ? ; c l = 50 pf; f i = 1 mhz; t r = t f = 2 ns; see figure 21 v cc = 1.65 v - 69 - mv v cc = 2.3 v - 87 - mv v cc = 3 v - 156 - mv v cc = 4.5 v - 302 - mv xtalk crosstalk between switches; r l = 600 ? ; c l = 50 pf; f i = 1 mhz; see figure 22 v cc = 1.65 v - ? 58 - db v cc = 2.3 v - ? 58 - db v cc = 3 v - ? 58 - db v cc = 4.5 v - ? 58 - db between switches; r l = 50 ? ; c l =5pf; f i = 1 mhz; see figure 22 v cc = 1.65 v - ? 58 - db v cc = 2.3 v - ? 58 - db v cc = 3 v - ? 58 - db v cc = 4.5 v - ? 58 - db table 11. additional dynamic characteristics ?continued at recommended operating conditions; voltag es are referenced to gnd (ground = 0 v); t amb =25 ? c. symbol parameter conditions min typ max unit 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 14 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch 10.2.1 test circuits q inj charge injection c l = 0.1 nf; v gen =0v; r gen = 0 ? ; f i = 1 mhz; r l =1 m ? ; see figure 23 v cc = 1.8 v - 3.3 - pc v cc = 2.5 v - 4.1 - pc v cc = 3.3 v - 5.0 - pc v cc = 4.5 v - 6.4 - pc v cc = 5.5 v - 7.5 - pc table 11. additional dynamic characteristics ?continued at recommended operating conditions; voltag es are referenced to gnd (ground = 0 v); t amb =25 ? c. symbol parameter conditions min typ max unit test conditions: v cc = 1.65 v: v i = 1.4 v (p-p). v cc = 2.3 v: v i = 2 v (p-p). v cc = 3 v: v i = 2.5 v (p-p). v cc = 4.5 v: v i = 4 v (p-p). fig 18. test circuit for measuring total harmonic distortion 001aag492 v ih v o v cc 0.5v cc nz/ny ny/nz ne 600 f i r l 10 f c l d adjust f i voltage to obtain 0 dbm level at output. increase f i frequency until db meter reads ? 3db. fig 19. test circuit for measuring the frequency response when switch is in on-state 001aag491 v ih v o v cc 0.5v cc nz/ny ny/nz ne 50 f i r l 0.1 f c l db 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 15 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch adjust f i voltage to obtain 0 dbm level at input. fig 20. test circuit for measuring isolation (off-state) 001aag493 v il v o v cc 0.5v cc nz/ny ny/nz ne 50 f i r l 0.5v cc r l 0.1 f c l db fig 21. test circuit for measuring crosstalk vo ltage (between digital inputs and switch) 001aag494 v o v cc 0.5v cc nz/ny ny/nz ne 50 600 logic input r l 0.5v cc c l g 20 log 10 (v o2 / v o1 ) or 20 log 10 (v o1 / v o2 ). fig 22. test circuit for measuri ng crosstalk between switches 001aag496 v ih 0.5v cc 1z or 1y 1y or 1z channel on 1e 50 600 f i r l r i 0.1 f c l 50 pf v o1 v il 0.5v cc 2z or 2y 2y or 2z channel off 2e r l r i 600 c l 50 pf v o2 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 16 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch q inj = ? v o ? c l . ? v o = output voltage variation. r gen = generator resistance. v gen = generator voltage. fig 23. test circuit for measuring charge injection 001aag495 v o v cc nz/ny ny/nz ne logic input r l 1 m r gen c l 0.1 nf v gen g mna675 on off logic input (ne) v o off v o 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 17 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch 11. package outline fig 24. package outline sot108-1 (so14) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 18 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch fig 25. package outline sot402-1 (tssop14) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 19 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch fig 26. package outline sot762-1 (dhvqfn14) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.65 1.35 y 1 2.6 2.4 1.15 0.85 e 1 2 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot762-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot762-1 dhvqfn14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 26 13 9 8 7 1 14 x d e c b a 02-10-17 03-01-27 terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 20 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch 12. abbreviations 13. revision history table 12. abbreviations acronym description cmos complementary metal oxide semiconductor ttl transistor-transistor logic hbm human body model esd electrostatic discharge mm machine model dut device under test mil military table 13. revision history document id release date data sheet status change notice supersedes 74lvc4066_q100 v.1 20120807 product data sheet - - 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 21 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 14.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 14.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. 74lvc4066_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 7 august 2012 22 of 23 nxp semiconductors 74lvc4066-q100 quad bilateral switch no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 14.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 15. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors 74lvc4066-q100 quad bilateral switch ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 7 august 2012 document identifier: 74lvc4066_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional description . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 recommended operating conditions. . . . . . . . 5 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 9.1 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.2 on resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9.3 on resistance test circuit and graphs. . . . . . . . 8 10 dynamic characteristics . . . . . . . . . . . . . . . . . 10 10.1 waveforms and test circuit . . . . . . . . . . . . . . . 11 10.2 additional dynamic characteristics . . . . . . . . . 12 10.2.1 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 14 legal information. . . . . . . . . . . . . . . . . . . . . . . 21 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 14.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 14.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 14.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 15 contact information. . . . . . . . . . . . . . . . . . . . . 22 16 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 |
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